Semiconductor device having an etch stopper formed of a SiN layer by low temperature ALD and method of fabricating the same

ABSTRACT

Provided are a semiconductor device having an etch stopper formed of a nitride film by low temperature atomic layer deposition which can prevent damage to a semiconductor substrate and a method for fabricating the semiconductor device. Damage to the semiconductor substrate under the etch stopper composed of a second nitride film can be prevented by forming a first nitride film using high temperature LPCVD on the semiconductor substrate, forming the etch stopper including the second nitride film by low temperature ALD on the first nitride film, and removing the second nitride film by dry etching, thus taking advantage of the different etch selectivities of the first nitride film and the second nitride film.

This application is a continuation of U.S. application Ser. No.10/612,028, filed on Jul. 2, 2003, which relies for priority upon KoreanPatent Application No. 02-55005, filed on Sep. 11, 2002, the contents ofwhich are herein incorporated by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method forfabricating the semiconductor device, and more particularly, to asemiconductor device having an etch stopper formed of a silicon nitride(SiN) layer by low-temperature atomic layer deposition (ALD) in aself-aligned contact (SAC) process and a method for fabricating thesemiconductor device.

2. Description of the Related Art

As a finer pattern and a thinner film are required in a process offabricating semiconductor devices, atomic layer deposition (ALD)technology beneficial for the finer pattern and the thinner film is morewidely applied to DRAM devices. In particular, ALD is useful foraccurately controlling the thickness of a film and thus is used to formcapacitor dielectric films, diffusion barriers, gate dielectric layers,and the like.

As semiconductor devices become highly integrated, the space betweengates becomes smaller, and thus a self-aligned contact (SAC) processhaving a design rule for the space of about 0.2 μm has been generallyused. The SAC process uses a gate pattern as an etch buffer so as tocause a short between a contact plug and the gate pattern due to amisalignment when a contact hole is formed in a source or a drainbetween gates. As a technique using the SAC process is introduced into amethod of fabricating the

FIG. 1 is a sectional view illustrating the SAC process according to theconventional art after a second etching is performed, and FIG. 2 is aenlarged view of area A of FIG. 1.

Referring to FIG. 1, a gate pattern 20 is formed on a semiconductorsubstrate 10, and an etch stopper 30 is deposited on the gate pattern20. Then, an interlayer insulating film 40 is formed on the gate pattern20 and the semiconductor substrate 10, and the interlayer insulatingfilm 40 is planarized. A photoresist pattern 50 is formed on theinterlayer insulating film 40, and a self-aligned contact hole 60 isformed by dry etching, exposing a source region and a drain region ofthe gate pattern 20.

In the dry etching for forming the self-aligned contact hole 60, anoxide film or a nitride film having a high etching selectivity with theinterlayer insulating film 40 formed of oxide film and formed by lowpressure chemical vapor deposition (LPCVD) is used as an insulatingpattern 26 on the upper side of the gate and a gate spacer 28 so as toprevent a gate electrode pattern 22 and a silicide pattern 24 of thegate pattern 20 from being etched.

In addition, when the self-aligned contact hole is dry etched, thenitride film formed by LPCVD is used as the etch stopper 30 so as toprevent damage to the semiconductor substrate 10 from etching. The etchstopper 30 is a thin film having a thickness of 100-200 Å and is removedby a second dry etch of which the etching conditions are different fromthe etching conditions of the dry etch for forming the self-alignedcontact hole, after dry etching the interlayer insulating film 40 toform the self-aligned contact hole.

However, in a second dry etching for the thin etch stopper 30 of theconventional self-aligned contact process, the semiconductor substrate10 is also etched, and thus a recess in or damage to the semiconductorsubstrate 10 results, as shown in FIG. 2. This is because the film to beetched is very thin, and a constant etching speed for the whole wafer isnot yet possible. Further, the thickness of the nitride film cannot becontrolled to be constant. In addition, since there are differencesamong equipment used for mass production, it is difficult toconsistantly etch thin films, a fact which causes further damage tosemiconductor substrates.

Damage to the semiconductor substrate 10 or a recess therein can causeAC parameter defects such as T_(RDL) (last data in to row precharge) inthe DRAM device chip at the center of the wafer which has been etchedless while degrading the refresh characteristics at the edge of thewafer which has been etched more. Thus, reliability and yield of thesemiconductor device are reduced.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor device having an etchstopper formed of a nitride film by low temperature atomic layerdeposition (ALD) so as to prevent damage to a semiconductor substrateand prevent a recess from forming therein.

The present invention also provides a method for fabricating asemiconductor device having an etch stopper formed of a nitride film bylow temperature ALD.

According to an aspect of the present invention, there is provided asemiconductor device having an etch stopper formed of a nitride filmusing low temperature atomic layer deposition, the semiconductor devicecomprising a gate pattern which is formed on the semiconductor deviceand composed of a top layer formed of a first nitride film using lowpressure chemical vapor deposition and a gate spacer. An etch stoppercovers the semiconductor substrate and the gate pattern and includes asecond nitride film formed using low temperature atomic layerdeposition. An interlayer insulating film is formed on the etch stopper.

According to a preferred embodiment of the present invention, it ispreferable that the etch stopper be formed at a temperature of 100 to500° C. and the thickness of the etch stopper be within 100 to 700 Å.

Preferably, the gate pattern of the semiconductor device comprises agate electrode which is formed on the semiconductor substrate andincludes polysilicon and a silicide layer which is formed on the gateelectrode. The top layer of the gate pattern is formed on the silicidelayer and includes the first nitride film formed using low pressurechemical vapor deposition. The gate spacer is formed on the sidewalls ofthe gate electrode, the suicide layer, and the top layer and includesthe first nitride film formed using low pressure chemical vapordeposition.

In addition, the interlayer insulating film can be a single film formedof an oxide film including one of SiO₂, BPSG, HDP oxide, and Fox, andthe interlayer insulating film can be a multi-layer film including filmscomposed of an oxide film including one of SiO₂, BPSG, HDP oxide, Fox.

According to another aspect, the present invention is directed to amethod for fabricating a semiconductor device having an etch stopperformed of a nitride film using low temperature atomic layer deposition.A gate pattern is formed on a semiconductor substrate. The gate patternincludes a first nitride film formed using low pressure chemical vapordeposition for a top layer and sidewalls. An etch stopper is formedcovering the gate pattern and the semiconductor substrate to apredetermined thickness and includes a second nitride film formed usinglow temperature atomic layer deposition. An interlayer insulating filmis deposited on the semiconductor substrate where the etch stopper isformed. A self-aligned contact hole is formed by dry etching theinterlayer insulating film by using the gate pattern as a mask. The etchstopper which is exposed to the self-aligned contact hole by wet etchingis removed.

According to a preferred embodiment of the present invention, formingthe gate pattern comprises depositing a gate electrode, a silicidelayer, and a top layer, which includes the first nitride film formedusing low pressure chemical vapor deposition, on the semiconductorsubstrate; etching the gate electrode, the silicide layer, and the toplayer; and forming the gate spacer, which is composed of the firstnitride film formed using low pressure chemical vapor deposition, on thesidewalls of the gate electrode, the silicide layer, and the top layer.

The second nitride film by the atomic layer deposition is formed at atemperature of 100 to 500° C., and the thickness of the second nitridefilm is within 100 to 700 Å.

Preferably, as a reaction gas for forming the etch stopper, one of SiH₄,SiCl₂H₂, and SiCl₄ is used as a silicon source, and one of N₂, NH₃, andN₂O is used as a nitrogen source.

In addition, the interlayer insulating film is a single layer filmformed of an oxide film including SiO₂, BPSG, HDP oxide, Fox, and theinterlayer insulating film is a multi-layer film including filmscomposed of an oxide film including SiO₂, BPSG, HDP oxide, Fox.

According to another preferred embodiment of the present invention, thedry etching for forming the self-aligned contact hole continues untilthe etch stopper is exposed. A hydrofluoric acid solution as an etchingsolution is used in the wet etching for removing the etch stopper. Thewet etching for removing the etch stopper employs a SC1 cleaning methodwhich is developed by RCA Inc.

According to the present invention, a recess occurring in and damage tothe semiconductor substrate can be prevented by using the first nitridefilm as an etch stopper. The first nitride film is formed of the samematerial as a top film and a gate spacer and the second nitride film,having a high etch selectivity and which is formed by low temperatureALD.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages of theinvention will be apparent from the more particular description of apreferred embodiment of the invention, as illustrated in theaccompanying drawings in which like reference characters refer to thesame parts throughout the different views. The drawings are notnecessarily to scale, emphasis instead being placed upon illustratingthe principles of the invention.

FIG. 1 is a sectional view illustrating a self-aligned contact (SAC)process according to the conventional art.

FIG. 2 is an enlarged view of area A of FIG. 1.

FIGS. 3 through 7 are sectional views illustrating a SAC process of asemiconductor device using a nitride film, formed by low temperatureALD, as an etch stopper, in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention now will be described more fully with reference tothe accompanying drawings, in which preferred embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as being limited to theembodiments set forth herein. Various embodiments may be implementedwithout departing from the spirit and the essential characteristics ofthe invention as defined by the appended claims. For example, in apreferred embodiment of the present invention, an etch stopper formed ofa second nitride film by low temperature atomic layer deposition (ALD)(i.e., under 500° C.) is applied or used on a gate pattern in a SACprocess. The second nitride film can also be used as an etch stopper inother processes. Therefore, the following examples are for illustrativepurposes and are not intended to limit the scope of the invention.

Referring to FIG. 5, a semiconductor device having an etch stopperformed of a nitride film by low temperature ALD will be described.

The semiconductor device having the etch stopper formed of the nitridefilm by low temperature ALD, according to the present invention,includes a semiconductor substrate 100 formed on a pad oxide film (notshown), a gate pattern 110 formed on the semiconductor substrate 100, anetch stopper 120 which covers the semiconductor substrate 100 and thegate pattern 110 in a blanket manner, i.e., conformally, and is a secondnitride film formed by ALD, and an interlayer insulating film 130 formedon the etch stopper 120. The gate pattern 110 includes a top layer 106formed of a first nitride film by low pressure chemical vapor deposition(LPCVD) and a gate spacer 108.

During dry etching to form a self-aligned contact hole 150 of FIG. 6 byetching the interlayer insulating film 130 formed of an oxide film, theetch stopper 120 functions well because it has an etch selectivity 1-1.3times higher than the etch selectivity of the top layer 106 and the gatespacer 108, which are composed of the first nitride film, of the gatepattern 110. Here, the top layer 106 and the gate spacer 108 are formedby LPCVD at a high temperature, i.e., over 600° C.

In addition, in a second wet etch process to remove the etch stopper120, the etch stopper 120 has an etch rate 20 times higher than the etchrate of the top layer 106 and the gate spacer 108, which are composed ofthe first nitride film, of the gate pattern 110 and has a low density.Thus, the etch stopper 120 can be removed without causing a recess inthe semiconductor substrate 100 or damage thereto.

Therefore, the etch stopper 120 formed of the second nitride film by thelow temperature ALD according to the present invention has a high etchselectivity to the oxide film, which composes the interlayer insulatingfilm 130, in dry etching and has a high etch selectivity to the firstnitride film by the high temperature LPCVD in wet etching.

Next, a SAC process of the semiconductor device having the etch stopperformed of the nitride film by low temperature ALD, according to thepresent invention, will be described with reference to FIGS. 3 through7.

Referring to FIG. 3, the gate pattern 110 is formed on the semiconductorsubstrate 100 where the pad oxide film is formed. Here, the gate pattern110 is formed by depositing a gate oxide film (not shown), a polysiliconfilm for a gate electrode 102, a silicide layer 104, and a first nitridefilm for the top layer pattern 106 on the semiconductor substrate 100and then forming the gate spacer 108 composed of the first nitride filmon the sidewalls of the resultant structure. The top layer pattern 106and the gate spacer 108 of the gate pattern 110 are composed of thefirst nitride film, which is formed by high temperature LPCVD, i.e.,over 600° C.

Referring to FIG. 4, the etch stopper 120 is formed to cover the gatepattern 110 and the whole semiconductor substrate 100 in a blanketmanner. That is, the etch stopper 120 is formed to conformally cover thegate pattern 110 and the whole semiconductor substrate 100. The etchstopper 120 is composed of the second nitride film formed by lowtemperature ALD (i.e., 100˜500° C.) and the appropriate thickness of theetch stopper 120 is 100-700 Å. The ALD for forming the second nitridefilm, i.e., the etch stopper 120, uses one of SiH₄, SiCl₂H₂, or SiCl₄ asa silicon source and one of N₂, NH₃, or N₂O as a nitrogen source. Thesecond nitride film can be formed at a lower temperature than the firstnitride film and has a low density. Consequently, the second nitridefilm functions well as the etch stopper 120 when patterning theinterlayer insulating film 130. In addition, the second nitride film,i.e., the etch stopper 120, is easily removed without causing a recessor damage to the lower film, e.g., the semiconductor substrate 100,during the wet etching.

Referring to FIG. 5, the interlayer insulating film 130 is formed on thesemiconductor substrate 100 where the etch stopper 120 is formed, toplanarize the semiconductor substrate 100. The interlayer insulatingfilm 130 is formed of a single layer film composed of an oxide filmincluding SiO₂, BPSG, HDP oxide, or Fox or of a multi-layer filmincluding a single layer film composed of an oxide film including one ofSiO₂, BPSG, HDP oxide, Fox. Here, a CMP (chemical mechanical polishing)process or a planarizing process such as reflow can be applied to theinterlayer insulating film 130, if necessary.

Referring to FIG. 6, a photoresist pattern 140 is formed on thesemiconductor substrate 100 where the interlayer insulating film 130 isformed and the interlayer insulating film 130 is dry etched, therebyforming a self-aligned contact hole 150. Here, the etch stopper 120composed of the second nitride film prevents the silicide layer 104 orthe gate electrode 102 from being etched in the dry etching for formingthe self-aligned contact hole 150 and prevents damage to thesemiconductor substrate 100.

FIG. 7 is an enlarged view of area B of FIG. 6 and shows the result ofapplying the dry etching to B.

Referring to FIG. 7, in contrast to the conventional art in which theetch stopper 120 is removed by dry etching, the composition of the etchstopper 120 is changed so that the etch stopper 120 is composed of thesecond nitride film formed by low temperature ALD, and the changed etchstopper 120 is removed by wet etching in the present invention. Here, ahydrofluoric acid (HF) solution may be used as an etching solution.Alternatively, SC1 (standard cleaning 1), which was developed by RCAInc., can be applied in the wet etching.

SC1 includes a step of cleaning for 10 minutes with a cleaning solutionat a temperature of 80° C., and composed of NH₄OH, H₂O₂ and H₂O in aratio of 1:1:5, rinsing with deionised water, cleaning by dipping in 1percent hydrofluoric acid (HF) solution, rinsing with deionised water,cleaning for 10 minutes with a cleaning solution at a temperature of 80°C. and, composed of HCl, H₂O₂, and H₂O in a ratio of 1:1:6, rinsing withdeionised water, and spin drying.

As described above, the first nitride film, which constitutes the toplayer and the gate spacer of the gate pattern in the SAC process, andthe second nitride film having a high selectivity in the wet etching,e.g., a film formed by low temperature ALD, are used as the etchstopper, thus a recess in the semiconductor substrate and damage theretocan be prevented.

While this invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention as defined by the appended claims and equivalents.

1. A method for fabricating a semiconductor device comprising: forming agate pattern on a semiconductor substrate in which the gate patternincludes sidewalls; forming an etch stopper which covers the gatepattern and the semiconductor substrate to a predetermined thicknessusing low temperature atomic layer deposition; depositing an interlayerinsulating film on the semiconductor substrate where the etch stopper isformed; forming a self-aligned contact hole by dry etching theinterlayer insulating film using the gate pattern as a mask; andremoving the etch stopper which is exposed to the self-aligned contacthole by wet etching.
 2. The method of claim 1, wherein said removing theetch stopper which is exposed to the self-aligned contact hole by wetetching is followed by the steps of: forming an interconnection on thesemiconductor device; and packaging the device in a semiconductor devicepackage.
 3. The method of claim 1, wherein the etch stopper comprises anitride film.
 4. The method of claim 1, wherein the gate patterncomprises a nitride film formed using low pressure chemical vapordeposition.
 5. The method of claim 4, wherein the etch stopper comprisesa second nitride film.
 6. The method of claim 1, wherein, as a reactiongas for forming the etch stopper, one of SiH₄, SiCl₂H₂, and SiCl₄ isused as a silicon source, and one of N₂, NH₃, and N₂O is used as anitrogen source.
 7. The method of claim 1, wherein the interlayerinsulating film is a single layer film formed of an oxide film includingSiO₂, BPSG, HDP oxide, Fox.
 8. The method of claim 1, wherein theinterlayer insulating film is a multi-layer film including filmscomprising an oxide film including SiO₂, BPSG, HDP oxide, Fox.
 9. Themethod of claim 1, wherein the dry etching for forming the self-alignedcontact hole continues until the etch stopper is exposed.
 10. The methodof claim 1, wherein a hydrofluoric acid solution as an etching solutionis used in the wet etching for removing the etch stopper.
 11. The methodof claim 1, wherein the wet etching for removing the etch stopperemploys a SC1 cleaning method.